A static random access memory (SRAM) typically includes an array of memory cells and peripheral circuits. Each cell generally comprises at least 6 transistors, a word line, and two bit lines. An SRAM is generally driven by low power and operates at reasonably high speeds. As the complementary metal oxide semiconductor (CMOS) technology continues to scale down in the submicron range, designing SRAM devices faces many complex challenges. Among these challenges, cell stability is one that must be addressed.
Cell stability relates to the ability of a cell to resist accidental overwrites during various operating conditions (e.g., noise due to transistor mismatch, threshold variations, etc.). In an SRAM array, cells can suffer from problems related to cell stability during Read/Write operations. Smaller current requires more time to develop a signal, making it harder to write into cell 100. On the other hand, when cell 100 is operating under a scenario in which both bitlines are near the supply voltage (Vdd) state and the wordline is on, data stored in the cell may be flipped unexpectedly.
FIG. 1 is a schematic representation of an exemplary CMOS six-transistor (6T) SRAM cell 100. Cell 100 uses six transistors (P0, P1, N0, N1, N2, N3) to store and access one bit. The four transistors in the center form two cross-coupled inverters (tru, cmp). For the sake of discussion, assuming that wordline wl switches on when the voltage of “tru” (Vtru) is high, the voltage of “cmp” (Vcmp) is low, and the voltage of bitlines (Vblt and Vblc) are high. When wl is off, P0 and N1 are on, and P1 and N0 are off. When wl is on, Vcmp is raised because Vblc is high. The amount raised is decided by the conductance ratio of transfer gate N3 and pull down device N1. If the amount is high enough to turn N0 on and turn P0 off, Vtru goes down slightly. This causes N1 turns slightly off and P1 turns slightly on, which enhances Vcmp (i.e., goes up) which, in turn, turns N0 on stronger than before. With this positive feedback mechanism, Vtru eventually settles to low and Vcmp eventually settles to high. As long as wl is kept low, cell 100 is disconnected from the bitlines and the inverters can keep feeding themselves, allowing cell 100 to store its current value. However, as described above, when cell 100 is exposed to a situation where wl is on and both bit and blc are near the Vdd state, the state of cell 100 may be flipped unexpectedly, destroying data stored therein.
In the SRAM array, cells can suffer from the aforementioned cell stability problems during both Read and Write operations, causing undesirable cell data destruction. In some cases, these cell stability problems may be addressed by modifying cell size, array structure (single column or multi-column), and/or access pattern (i.e., during Read or Write operation). Some prior attempts are described below with reference to FIG. 2-FIG. 8.
FIG. 2 is a schematic representation of an exemplary 6T SRAM array 200 having a single-column structure. In this structure, each column has an input, a Read Circuit, a Write Circuit, and an output.
An exemplary Read operation can be performed as follows. First, the bitlines are precharged to high. Then, the precharge device is turned off and the wordline is turned on. Each memory cell pulls either of the bitlines down, depending upon whether “0” or “1” had been stored inside the cell. Read Circuit senses the voltage on the bitline and outputs the data. Then, the wordline shuts off. In some cases, in a Read operation, SRAM cell 100 may be exposed to a state where both bitline voltages are near the power supply voltage (Vdd) right after the wordline is turned on, causing a cell stability problem as described above.
An exemplary Write operation can be performed as follows. First, the bitlines are precharged to high. Then, the precharge devices are turned off and the wordline is turned on. Write Circuit pulls either of the bitlines down. The voltage on the bitline is transferred to a memory cell through its transfer gate. The state of the flip-flop in the memory cell settles. Then, the wordline shuts off. Because an activated cell is eventually written (i.e., overpowered) by Write Circuit in 6T SRAM array 200, cell stability is not a cause for concern during the Write operation.
FIG. 3 is a schematic representation of an exemplary 6T SRAM array 300 having a multi-column structure. In this structure, there are m columns and an m-to-1 multiplexer (m:1 MUX) is used to select a column. The Read and Write operations can be performed in basically the same manner as described above with reference to FIG. 2. One difference is that, when a certain column is accessed, all the other columns would be affected by the cell stability problem in both the Read and Write operations. For example, assume that a Write happens to column 1 (col_1). First, the bitlines for columns are precharged to high. Then, the precharge device is turned off and the wordline is turned on. Write Circuit pulls either of the bitlines of col_1 down. At this moment, the voltage of the bitlines of all neighboring columns (col_2 to col_m) are all near Vdd and the wordline is on, which means that they have a cell stability problem. Similarly, in a Read operation, not only the accessed column but also the unselected columns will have this cell stability problem.
Some have tried to use 8T and 10T SRAM cells to address the cell stability problem in the Read operation. FIG. 4 is a schematic representation of an exemplary 8T SRAM cell 400. FIG. 5 is a schematic representation of an exemplary 10T SRAM cell 500. In both cases, wwl is used for the Write operation, and rwl is used for the Read operation. When rwl is on, the voltage of node “tru_r” is raised, but this does not propagate to node “cmp”. This means that the positive feedback mechanism, which causes a 6T SRAM cell to be unstable as described above, is absent in 8T and 10T SRAM cells during the Read operation.
FIG. 6 is a schematic representation of an exemplary 8T SRAM array 600 having a single-column structure. An exemplary Read operation can be performed as follows. First, the bitlines are precharged to high. Then, the precharge device is turned off and the read wordline (rwl) is turned on. Each bitline is pulled down or stays high according to cell data stored therein. Read Circuit senses the voltage on the bitline and outputs the data. Then, the wordline shuts off. As described above, each 8T SRAM cell in array 600 can avoid the cell stability problem in the Read operation. An exemplary Write operation can be performed as follows. First, the bitlines are precharged to high. Then, the precharge device is turned off and the wordline is turned on. Write Circuit pulls either of the bitlines down. The voltage on the bitline is transferred to a memory cell through its transfer gate, and the state of the flip-flop in the memory cell settles. Then, the wordline shuts off. Because an activated cell is eventually written by Write Circuit, cell stability is not a cause for concern for 8T SRAM array 600 during the Write operation.
FIG. 7 is a schematic representation of an exemplary 8T SRAM array 700 having a multi-column structure. In this structure, there are m columns and an m-to-1 multiplexer (m:1 MUX) is used to select a column (e.g., via colsel). The Read and Write operations can be performed in basically the same manner as described above with reference to FIG. 6. One difference is that, when a certain column is accessed, all the other columns would be affected by the cell stability problem in the Write operation. For example, assume that a Write happens to column 1 (col_1). First, the bitlines for columns are precharged to high via a precharge device (pc). Then, pc is turned off and the wordline is turned on. Write Circuit pulls either of the bitlines of col_1 down. At this moment, the voltage of bitlines of the other columns (col_2 to col_m) are all near Vdd and the wordline is on, indicating a cell stability problem. As described above, in a Read operation, all columns of 8T SRAM cells are free from the cell stability problem.
FIG. 8 is a schematic representation of an exemplary 10T SRAM array 800 having a multi-column structure. 10T SRAM array 800 comprises an array of 10T SRAM cells and operates basically in the same manner as 8T SRAM array 700. Each 10T SRAM cell can be similarly structured to perform like cell 500 described above with reference to FIG. 5.
To summarize, cell stability remains problematic in at least the following scenarios: during the Read operation in 6T SRAM arrays having a single-column structure; during the Read and Write operations in 6T SRAM arrays having a multi-column structure; and during the Write operation in 8T and 10T SRAM arrays having a multi-column structure. There is a need in the art to solve the cell stability problems represented in these scenarios. Embodiments of the present invention can address this need and more.